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| HV20420 HV20620 Low Charge Injection 8-Channel High Voltage Analog Switch Ordering Information Package Options VPP - VNN 200V 200V 28-pin plastic DIP HV20420P - 28-lead plastic chip carrier HV20420PJ HV20620PJ Die HV20420X - Features s HVCMOS technology for high performance (R) General Description Not recommended for new designs. Please use HV202 instead. This device is a low charge injection 8-channel high-voltage analog switch integrated circuit (IC) intended for use in applications requiring high voltage switching controlled by low voltage control signals, such as ultrasound imaging and printers. Input data is shifted into an 8-bit shift register which can then be retained in an 8-bit latch. To reduce any possible clock feedthrough noise, Latch Enable Bar (LE) should be left high until all bits are clocked in. Using HVCMOS technology, this switch combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. This IC is suitable for various combinations of high voltage supplies, e.g., VPP/VNN : +50V/-150V, or +100V/-100V. The specifications for the HV204 and HV206 are identical except that the pinouts in the 28-lead plastic chip carrier are different. s Low charge injection s Very low quiescent power dissipation - 10A s Output On-resistance typically 22 ohms s Low parasitic capacitances s DC to 10MHz analog signal frequency s -60dB typical output off isolation at 5MHz s CMOS logic circuitry for low power s Excellent noise immunity s On-chip shift register, latch and clear logic circuitry s Flexible high voltage supplies s Surface mount package available Absolute Maximum Ratings* VDD Logic power supply voltage VPP - VNN Supply voltage VPP Positive high voltage supply VNN Negative high voltage supply Logic input voltages Analog Signal Range Peak analog signal current/channel Storage temperature Power dissipation -0.5V to +18V 220V -0.5V to VNN +200V +0.5V to -200V -0.5V to VDD +0.3V VNN to VPP 3.0A -65C to +150C 1.2W * Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. 13-32 HV20420/HV20620 DC Characteristics (over recommended operating conditions unless otherwise noted) 0C Characteristics Small Signal Switch (ON) Resistance Sym min max 30 25 25 18 Small Signal Switch (ON) Resistance Matching Large Signal Switch (ON) Resistance Switch Off Leakage Per Switch DC Offset Switch Off DC Offset Switch On Pos. HV Supply Current Neg. HV Supply Current Pos. HV Supply Current Neg. HV Supply Current Switch Output Peak Current Output Switch Frequency fSW 8.1 IPP Supply Current IPP 5.0 8.1 INN Supply Current Logic Supply Average Current Logic Supply Quiescent Current Data Out Source Current Data Out Sink Current Logic Input Capacitance INN IDD IDDQ ISOR ISINK CIN 0.45 0.45 10 5.0 6.0 10 0.45 0.45 0.70 0.70 10 4.0 IPPQ INNQ IPPQ INNQ 3.0 RONS RONL ISOL 5.0 300 500 20 min +25C typ 26 22 22 18 5.0 15 1.0 100 100 10 -10 10 -10 3.0 10 300 500 50 -50 50 -50 2.0 50 8.8 6.3 8.8 6.3 6.0 10 0.40 0.40 10 10.0 6.9 10.0 6.9 6.0 10 mA mA A mA mA pF VOUT = VDD - 0.7V VOUT = 0.7V mA 2.0 15 300 500 max 32 27 27 20 20 +70C min max 35 32 30 23 20 % ohms A mV mV A A A A A KHz ohms Units Test Conditions ISIG = 5mA ISIG = 5mA VPP = + 50V, VPP = +100V, Electrical Characteristics RONS ISIG = 200mA VNN = -150V ISIG = 200mA VNN = -100V ISW = 5mA, VPP = +100V, VNN = -100V VSIG = VPP - 10V, ISIG = 1.0A VSIG = VPP - 10V to VNN +10V RL = 100K RL = 100K ALL SWs OFF ALL SWs OFF ALL SWs ON ISW = 5mA ALL SWs ON ISW = 5mA VSIG duty cycle 0.1% Duty Cycle = 50% VPP = +50V, VNN = -150V VPP = +100V, VNN = -100V VPP = +50V, VNN = -150V VPP = +100V, VNN = -100V fCLK = 3MHz 50KHz Output Switching Frequency with no load 13 13-33 HV20420/HV20620 Electrical Characteristics AC Characteristics (over operating conditions VDD = 15V, unless otherwise noted) 0C Characteristics Time to Turn Off VSIG* Set Up Time Before LE Rises Time Width of LE Clock Delay Time to Data Out Time Width of CL Set Up Time Data to Clock Hold Time Data from Clock Clock Freq Turn On Time Turn Off Time Maximum VSIG Slew Rate Sym tSIG(OFF) tSD tWLE tDO tWCL tSU tH fCLK tON tOFF dv/dt 13 -30 Off Isolation KO -45 Switch Crosstalk Output Switch Isolation Diode Current Off Capacitance SW to GND On Capacitance SW to GND Output Voltage Spike KCR IID CSG(OFF) CSG(ON) +VSPK -VSPK *Time required for analog signal to turn off before output switch turns off. min max min 0 +25C typ max min +70C max Units ns Test Condition 150 150 175 150 15 35 5.0 5.0 5.0 150 150 175 150 15 35 5.0 5.0 5.0 13 8.0 150 150 190 150 20 35 5.0 5.0 5.0 ns ns ns ns ns ns MHz s s 50% duty cycle fDATA = fCLK/2 VSIG = VPP - 10V VSIG = VPP - 10V VPP = +50V VNN = -150V V/ns VPP = +100V VNN = -100V f = 5.0 MHz, 1K//15pF load f = 5MHz, 50 load f = 5MHz, 50 load 300ns pulse width, 2.0% duty cycle 0V, 1MHz 0V, 1MHz VPP = +100V VNN = -100V RL = 50 -30 -45 -60 300 -33 -60 -70 300 -30 -45 -60 300 5.0 25 17 50 dB dB dB mA pF pF mV -60 5.0 25 17 50 5.0 25 12 38 150 150 17 50 Operating Conditions* Symbol VDD VPP VNN VIH VIL VSIG TA Notes: 1 Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2 VSIG must be VNN VSIG VPP or floating during power up/down transistion. 3 Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec. Parameter Logic power supply voltage1,3 supply1,3 supply1,3 Value 10.0V to 15.5 V 50V to VNN+ 200V -100V to -150V VDD -2V to VDD 0V to 2.0V Positive high voltage Negative high voltage High-level input voltage Low-level input voltage Analog signal voltage peak to peak2 VNN +10V to VPP -10V 0C to 70C Operating free air-temperature 13-34 HV20420/HV20620 Truth Table D0 L H L H L H L H L H L H L H L H X X D1 D2 D3 D4 D5 D6 D7 LE L L L L L L L L L L L L L L L L H X CL L L L L L L L L L L L L L L L L L H SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON HOLD PREVIOUS STATE OFF OFF OFF OFF OFF OFF OFF OFF Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L H transition CLK. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flows through the latch. 4. DOUT is high when switch 7 is on. 5. Shift register clocking has no effect on the switch states if LE is H. 6. The clear input overrides all other inputs. X X X X X X X X X X X X X X Test Circuits VPP -10V VPP -10 ISOL RL 10K VOUT VOUT VNN +10 100K RL VPP VNN VPP VNN VDD GND 15V VPP VNN VPP VNN VDD GND 15V VPP VNN VPP VNN VDD GND 15V Switch OFF Leakage DC Offset ON/OFF TON /TOFF Test Circuit 13 VIN = 10 VP-P @5MHz +VSPK VOUT -VSPK 50 NC VIN = 10 VP-P @5MHz 50 50 1K VOUT RL VPP VNN VPP VNN VDD GND VOUT VIN 15V VPP VNN VPP VNN VDD GND 15V VPP VNN VPP VNN VDD GND VOUT VIN 15V KO = 20Log KCR = 20Log OFF Isolation Output Voltage Spike Crosstalk 13-35 HV20420/HV20620 Logic Timing Waveforms DN - 1 DATA IN 50% DN 50% DN + 1 LE 50% 50% tWLE tSD 50% tSU th tDO 50% CLOCK DATA OUT 50% tOFF tON VOUT (TYP) OFF ON 90% 10% CLR 50% tWCL 50% Logic Diagram LATCHES DIN D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL LEVEL SHIFTERS OUTPUT SWITCHES SW0 CLK SW1 SW2 SW3 8 BIT SHIFT REGISTER SW4 SW5 DOUT SW6 SW7 VNN VPP VDD LE CL 13-36 HV20420/HV20620 Pin Configurations HV204 28-Pin DIP Pin Function 1 SW3 2 SW3 3 SW2 4 SW2 5 SW1 6 SW1 7 SW0 8 SW0 9 N/C 10 VPP 11 N/C 12 VNN 13 GND 14 VDD Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Function N/C DIN CLK LE CL DOUT SW7 SW7 SW6 SW6 SW5 SW5 SW4 SW4 HV204 28-Pin J-Lead Pin Function 1 SW3 2 SW3 3 SW2 4 SW2 5 SW1 6 SW1 7 SW0 8 SW0 9 N/C 10 VPP 11 N/C 12 VNN 13 GND 14 VDD Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Function N/C DIN CLK LE CL DOUT SW7 SW7 SW6 SW6 SW5 SW5 SW4 SW4 Package Outlines 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 HV204 22 21 20 19 18 17 16 15 top view 28-pin DIP 25 24 23 22 21 20 19 18 HV206 28-Pin J-Lead Pin Function 1 SW3 2 SW3 3 SW2 4 SW2 5 SW1 6 SW1 7 SW0 8 SW0 9 N/C 10 VPP 11 N/C 12 VNN 13 N/C 14 GND Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Function VDD DIN CLK LE CL DOUT SW7 SW7 SW6 SW6 SW5 SW5 SW4 SW4 26 27 28 1 2 3 4 5 6 7 8 9 10 11 HV204, HV206 17 16 15 14 13 12 13 top view 28-pin J-Lead Package 13-37 |
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